Bidirectional static counter controlled by counting signals and auxiliary counting signals



Dec. 5, 1967 D. PETZOLD 3,356,953

BIDIRECTIONAL STATIC COUNTER CONTROLLED BY COUNTING SIGNALS ANDAUXILIARY COUNTING SIGNALS Filed April 5, 1965 8 Sheets-Sheet 1 t m 's ns t 's m s l & l E 42 l m V V V5 V I 8 G v i v '1 i I v 1 A3 A3 A2 A2 A]A] A0 A0 Inve tor:

Dec. 5, 1967 D. PETZOLD 3,356,953

BIDIRECTIONAL STATIC COUNTER CONTROLLED BY COUNTING SIGNALS ANDAUXILIARY COUNTING SIGNALS Filed April .3, 1965. 8 Sheets-Sheet. 2

Inv for: eter itzold Dec. 5, 1967 D. PETZOLD 3,356,

BIDIRECTIONAL STATIC COUNTER CONTROLLED BY COUNTING SIGNALS ANDAUXILIARY COUNTING SIGNALS Filed April 5, 1965 8 Sheets-Sheet 5 & &h (in:33 5:

Inventor: new Emu Dec. 5, 1967 D. PETZOLD 3,356,953

BIDIRECTIONAL STATIC COUNTER CONTROLLED BY COUN'l'lNG SIGNALS ANDAUXILIARY COUNTING SIGNALS Filed April 5, 1965 8 Sheets-Sheet 4 Dec. 5,1967 D. PETZOLD 3,356,953

BIIJIRECTIONAL STATIC COUNTER CONTROLLED BY JOUNLING SIGNALS ANDAUXILIARY COUNTING SIGNALS Filed April I), 1965 8 Sheets-Sheet. i;

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Dec. 5, 1967 D. PETZOLD BIDIRECTIONAL STATIC COUNTER CONTROLLED BYCOUNTING SIGNALS AND AUXILIARY COUNTING SIGNALS Filed April 5, 1965 8Sheets-Sheet 6 Fig.8

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Dec. 5, 1967 D. PETZOLD 3,356,953

BIDIRECTIONAL STATIC COUNTER C(INT'ROLLED BY COUNTING SIGNALS ANDAUXILIARY COUNTING SIGNALS Filed April 1965 8 Sheets-Sheet Kg A0 etzo/dHttnmey ieier Invgntor:

Dec. 5, 1967 D. PETZOLD 3,356,953

BIDIRECTIONAL STATIC COUNTER CONTROLLED BY COUNTING SIGNALS ANDAUXILIARY COUNTING SIGNALS Filed April 5, 1965 8 Sheets-Sheet. 8

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t zold I Di ha- I -I I t; t, e I AW United States Patent 15 Claims. (a.328-44) ABSTRAKIT OF THE DliSCLQSURE A static counter for countingforward or backward and controlled by counting signals and auxiliarycounting signals which do not change their state simultaneously. Thecounter has binary stages each having a main store and an auxiliarystore. Each stage except the lowest-order stage is connected to theimmediately preceding stage in such a way that the output signalproduced by the auxiliary store of each counter stage changes its statein the middle of the output signal produced by the main store of therespective counter stage and in the middle of the time interval betweenthis main store output signal and the subsequent output signal of themain store, and also in such a way that the signals which produce theoutputs of each main store and each auxiliary store and which are putout by the input stages of the respective main and auxiliary storesoverlap each other.

The present invention relates to static counters. There exist dividerstages, such as so-called static flip-flops, each of whose counterstages comprises two' stores which are D.C.-connected to each other, thei stage being controlled by the (i1) stage. The counting signals appliedare a signal 1 and its negate '15. Such counters have discontinuities,as a result of which the individual stores may assume incorrect counts.

My copending application Serial No. 327,585, filed Nov. 29, 1963,discloses a static counter which incorpo rates counter stages eachhaving two memory units, namely, a main storage unit or so-called mainstore which puts out the signal of the particular digit represented bythe counter stage and an auxiliary storage unit or so-called auxiliarystore which coacts with the main store. The main and auxiliary storesare controlled by counting sig nals t and auxiliary counting signals tthere being time intervals between these signals. The signals areapplied in parallel to all of the counter stages. Such counters are freeof discontinuities, i.e., the individual partial signals produced by theinput stages of the stores overlap each other. Here, the input stagesare divided into setting and holding stages. A holding stage has thecharacteristic feature that the output of the store pertaining to vthisstage is fed back to such stage. The other input stages of this store,namely, the stages to which the output of this store is not fed back,are setting stages.

The output of a store becomes L (L being used to represent the binaryone) when the output of a setting stage is L. The output signal of astore is held at L if the output signal L of the store can be held by aholding stage throughout the time interval during which the settingstage produces a signal L. If a plurality of holding stages areprovided, the partial signals produced thereby have to overlap.

In the case of a parallel-controlled counter, no new counting signalsand auxiliary counting signals can be applied to the counter prior tothe expiration of the time it takes for the various switching steps,triggered by the counting signals and/or auxiliary counting signals,that occur in the counter stages to have run their course. However, thegreater the number of counter stages, the longer will be the timerequired for the running off of all of the logic steps, which, in turn,means that the greater the number of counter stages, the lower will bethe maximum counting frequency, because no new counting signals orauxiliary counting signals can be applied while the counting steps,triggered by previous signals, are still going on in the counter.

It is, therefore, the primary object of the present invention to providea counter arrangement which overcomes the above drawbacks, namely, toprovide a D.C.-coupled counter, free of discontinuities, which counterincorporates a plurality of counter stages each having a main store andan auxiliary store and which is controlled by counting signals andauxiliary counting signals which do not change their statesimultaneously, but which counterin contradistinction to theabove-described, parallelly controlled counter-can have a new countingsignal or auxiliary counting signal applied to it even before thecounting steps triggered by a previous counting signal or auxiliarycounting signal have completed their run through all of the counterstages. Such a counter can be used to advantage if the counting signalsappear at such a high rate that, but for the present invention, thecounting and auxiliary counting signals should first he stepped down,e.g., in a divider, and only then applied to a parallelly controlledcounter.

With the above objects in view, the present invention resides,basically, in a static counter which is capable of counting forward orbackward, which may be equipped with means that allow the counter to bepreset to any desired binary number, and which may also be provided withmeans for converting the counter into a decimal counter, this counterhaving a plurality of counter stages each incorporating a main store andan auxiliary store and controlled by means of counting signals andauxiliary counting signals which do not change their respective statessimultaneously, i.e., a counter as described in the mentionedapplication Serial No, 327,585. According to the present invention, eachi (i=1, 2, 3 counter stage that is to say, each counter stage other thanthe 0 of lowest-order counter stage is controlled by the (il) counterstage in such a manner that the output signal produced by an auxiliarystore changes its state in the middle of the output signal produced bythe corresponding main store and in the middle of the time gap betweenthis output signal of the main store and the subsequent output signal ofthis main store, and that the signals which produce the output signalsof each main and auxiliary store and which are put out by the inputstages pertaining to the main and auxiliary stores, overlap each other.

According to a further feature of the present invention, the main andauxiliary stores of the i counter stages each comprise an input settingstage and three input holding stages. Each of the main and auxiliarystores of the 0 stage, if the counter is controlled by counting signalst and auxiliary counting signals t which appear with time gaps betweenthem, comprises one setting stage and two holding stages; if the counteris controlled by overlapping counting signals 1- and auxiliary countingsignals 72, the main and auxiliary stores of the 0 stage each comprisesone setting stage and three holding stages. The input holding stages maybe replaced by an erasing stage which has a number of inputs equal tothe number of replaced input holding stages.

According to a still further feature of the present invention, the mainand auxiliary stores of the binary digit 2 will, if the counter hasapplied to it the counting sig- Patented Dec. 5, 1967 '5 J) nals and,auxiliary counting signals t t which have a time gap between them, havethe following logic functions:

(t &H&Z2)V(A0&H0&L)V(A &t1&L) =A0 Ca 0 2) o o z) o b z)= o or, if theapplied counting and auxiliary signals r 1 partially overlap each other,the following logic functions: (1'1&;IZ&HQ&ZZ)V(AO&FIO&Z)V(AO&T1&L)

V(AO&TZ&L)=AD with the main and auxiliary stores of the subsequent istages having the following logic functions:

t =counting signal ve app g t =auxiliary counting signal .2clear-for-counting signal n counting signal overlapping. r =aux1liarycounting signal A=output signal of the main store H =output signal ofthe auxiliary store L =erase signal a stage, i=2, 2 2

According to a still further feature of the present invention, the mainand auxiliary stores can be converted to have the following logicfunctions, with A and H representing the outputs of the main andauxiliary stores of the 2 stage and A, and H the outputs of the main andauxiliary stores of the higher-order stages:

According to a still further feature of the present invention, thecounter is adapted so as to be susceptible to being pre-set, this beingdone by providing all main stores, and the auxiliary stores beginningwith binary digit 2 with input logic circuits, the logic circuitspertaining to the main stores being controllable by presetting signals kand a common clear-for-presetting signal 1. The counter stages of such apresettable counter will then have the following functions,with A and Hagain representing the outputs of the main and auxiliary stores of the 2stage and A, and H, the outputs of the main and auxiliary stores of thehigher-order stages:

01 1170 112) v maho v trial) v (f o) o (!2&A0&Z2) v 0 0 2) 0 2 z2) =H0The element (f&A &A, maybe eliminated from the auxiliary store in thebinary digit 2 Additional objects and advantages of the presentinvention will become apparent upon consideration of the followingdescription when taken in conjunction with the accompanying drawings inwhich:

FIGURE 1 is a schematic circuit diagram showing one embodiment of aforward counting counter according to the present invention.

FIGURES 2a, 2b and 2c are time plots showing the timed relationshipbetween the various signals used to control the counter of FIGUREl andput out by the counter.

FIGURE 3 is a schematic circuit diagram showing another embodiment of aforward counting counter according to the present invention.

FIGURE 4 is a schematic circuit diagram showing a presettable counteraccording to the instant invention.

FIGURE 5 is a time plot showing the operation of the presettable counterof FIGURE 4.

FIGURE 6 is a schematic circuit diagram showing a backward countingcounter according to the present invention.

FIGURE 7 is a schematic circuit diagram of another embodiment of abackward counting counter according to the instant invention.

FIGURE 8 is a time plot showing the operation of the counters of FIGURES6 and 7.

FIGURE 9 is a schematic circuit diagram of one decade of a forwardcounting decimal counter according to the present invention.

FIGURE 10 is a time plot showing the operation of the decimal counter ofFIGURE 9.

FIGURE 11 is a schematic circuit diagram showing the lowest-ordercounter stage which is suitable for use when the counter is controlledby overlapping counting signals and auxiliary counting signals.

FIGURE 12 is a schematic circuit diagram of a binary counter of the typeshown in application Serial No.-

327,585, thereby to facilitate the explanation of the present invention.

FIGURES 13a, 13b, 13c and 13d are time plots showing the timedrelationship between various signals in the counter of FIGURE 12.

FIGURES 14a, 14b, 14c and 14d are, respectively, schematic circuitdiagrams of means for producing signals used in the counter of FIGURE12.

In each of the various circuit diagrams, the AND-circuits areidentifiedby & (in some cases with subscripts) and the OR-circuits by v, and ineach case the black bar represents the presence of an inverse orcomplement, i.e., a negated, output. Various ones of the circuits alsoinclude pure inverter or so-called NOT-circuits, these being circuits atwhich the output is the inverse that is to say, the negate, orcomplement, of the input, namely, 0 when the input is L, and L when theinput is 0.

In the time plots, for some of the signals, only the afiirmative signalsare shown, in the interest of simplicity and clarity. That is to saythat, for example, only the the accompanying drawings. FIGURE 12 showsthe first four counter stages of a binary counter made up of identicalcounter stages, each incorporating a main store S and an auxiliary storeS Each store is identified by an appropriate subscript, e.g., S 8 Thestores are constituted by input AND-circuits whose outputs are connectedto OR/NOT/NOT-circuits. All of the stores are galvanically coupled toeach other. The configuration or wave shape of the applied input signalsis of no consequence; all that is necessary is that the input signalshave certain predetermined amplitudes.

There will now be described the operation of the counters as well as thesignificance of the various signals.

The counter has applied to the actual counting signals t as well asauxiliary counting signals t the signals t and t being staggered ortime-shifted with respect to each other, i.e., the signals t and t occurat different times and, as shown graphically in FIGURE 13a, there aretime intervals between the signals t and t The signals themselves, aswell as the time intervals therebetween, may be diiferent durations. Ifthe timed relationship between the signals t and t is as depicted inFIGURE 13b, t can be used as the counting signal andT as the auxiliarycounting signal. If the timed relationship between the signals t and tis as shown in FIGURE 13c, two AND-circuits can be used for producingtwo signals (r 855) and t M which are staggered with respect to eachother and between which there is a time interval. The repeateddisappearance and reappearance of the t-signalsas depicted in FIGURE 13dand as might be produced by shocks or vibrations to which the pulsegenerator is subjected-will not adversely influence the operation. Thesignal trains identified in FIGURE 13d at a, (i=1, 2, 3, will each beconsidered, by the counter, as one counting signal, comparable to thesignals al of FIGURE 13a. The same applies to the signal trains b eachof which will be considered by the counter as an auxiliary countingsignal.

The A-signals represent the number of counting signal-s t registered bythe counter. The I-I-signals are auxiliary signals which are formed bythe counter itself and which assist the function of the counter. Asexplained above, the A-signals and H-signals of the binary counter areidentified by subscripts. The signal A of the binary counter thus hasthe value 2 Before the start of a counting operation, the counter is putinto a definite starting position by means of an erase or reset signalL=L. During the counting operation, the reset signal L=0. For purposesof simplification, those signals which in each counter stage togetheract on one AND-stage, are separately combined. The counter thereforehave applied to them t'-signals which are derived from the t-signals andthe negated reset signal Z by means of the circuits shown in FIGURES14a, 14b, 140. The e-signal produced by the circuit of FIGURE 14d isprovided solely so that the auxiliary store of the counter stage of thelowest order is constituted by circuitry similar to that of theauxiliary stores of the higher-order counter stages. The circuit shownin FIGURE 14d comprises two input AND-circuits whose outputs areconnected to an OR/NOT-circuit. One of the AND-circuits has applied toit the negate of a counting command signal z by means of which thecounter is made to count (when z=L) or not to count (when 2:0). (Thesignal input AND- circuit just referred to, as well as othersingle-input logic circuits which are part of circuitry referred tothroughout the following description, are provided for purposes ofelectrical symmetry.) The other AND-circuit has applied to it thesignals A and t2. The signal Z1 is derived from the z-signal, which mayappear at any time, and a signal 2 is derived from the signalz such thatZ can change its state only at the start of .an auxiliary countingsignal t as explained in the mentioned application Serial No. 327,585.The signal Z2 serves. as a clear-for-counting signal, i.e., the z-signals are counted only so long as z =L. So long as z =0, the counterremains at whatever count it has reached. The counter can be preset toany desired starting number by means of preset signals k, the same beingidentified by subscripts and superscripts in a manner analogous to thatin which the A and H signals are identified, as explained above. Thek-signals are accepted by the counter when a clear-for-presetting signalf=L. Since the f-signal disappears at the start of the countingoperation, a new number to which the counter may later be preset can bemade ready during the counting operation. If no presetting is required,the means by which the presetting is accomplished can be dispensed with.

Referring next to FIGURE 1 of the drawings, the same is a schematiccircuit diagram of one embodiment of a counter in accordance with thepresent invention, the same being a forward counting binary counterhaving, in the illustrated example, four counter stages, each having amain store S and an auxiliary store S The main and auxiliary storescomprise input AND-circuits & whose outputs are connected toOR/NOT-circuits v whose outputs are connected to inverter orNOT-circuits, the output of each of the latter being applied to at leastone of the input AND-circuits of the respective store. Beginning withthe binary digit 2 each of the stores has one setting AND-circuit 81 &respectively, and three holding AND-circuits 8t & respectively. Theoutput of each store is applied, in each case, to the holding circuits.The main and auxiliary stores of the lowest-order stage each have oneless stage than the main and auxiliary stores of the higher-orderstages. The stores of only the lowest-order stage have the countingsignals and auxiliary counting signals t and t applied to them, thesecounting signals and auxiliary counting signals being staggered andthere being time intervals between them, as shown in the time plot ofFIGURE 2. Alternatively, the stores of the lowestorder stage can haveapplied to them overlapping counting where A=output signals of the mainstores H=output signals of the auxiliary stores t =counting signals t=auxiliary counting signals z =clear-for-counting signals L=erasesignal.

FIGURES 2a and 2b are time plots showing the opera tion of the counterof FIGURE 1. The right-hand portion of FIGURE 2a of the time plot showstwo interruptions in the counting operation (2:0). If the signals t andt are used for controlling the lowest-order stage, the same will haveonly two holding conditions, while if overlapping signals 1- T2, areapplied to the lowest-order counter stage, the same will have threeholding conditions. The circuity of the lowest-order counter stagesuitable for use with overlapping signals 1- T2, is shown in FIGURE 11,and such a circuit arrangement will operate in accordance with thefollowing logic functions:

signals of the main stores while the H-signals represent the outputsignals of the auxiliary stores. The purpose 7 of the H-signals is todistinguish between the leading and trailing flanks of the A-signals Atthe instants at which the A-signals appear, the H-signals are, forexample, 0, and at the instants at which the A-signals disappear theH-signals are L. According to the present invention, the H-signalschange their state precisely in the middle of the A-signals and, subjectto the exception noted below, in connection with the decimal counterwhich will be described in conjunction with FIGURE 9, also precisely inthe middle of the time interval between two A-signals. The A-signals andH-signals are put out by stores which have logic input circuits at whoseoutputs overlapping signals will appear. It is this appearance of theH-signals in conjunction with the generation thereof from overlappingpartial signals which is the salient feature of the counter according tothe present invention. The A-signals will double their duration, fromstage to stage. The same applies to the H-signals. The lower part ofFIGURE 2a shows the signals which appear at the outputs A of the mainstores. These output signals represent a backward counting as the timeplot shows.

FIGURE 2b shows how the signals A and H are combined from the partialsignals, the time plots showing the output signals of the setting andthe three holding stages. It will thus be seen that the A and H signalsare free of any discontinuities.

FIGURE 3 is a schematic circuit diagram of a modified counter inaccordance with the present invention, the same also being a forwardcounting binary counter and operating in accordance with the same timeplots as described in conjunction with the counter of FIGURE 1, i.e.,the time plot shown in FIGURES 2a and 2c. Each counter stage againcomprises main and auxiliary stores S and S which, however differ fromthe stores of the counter of FIGURE 1 in that the stores of the counterof FIGURE 3 each have but one input setting stage 8: 8: and one inputerase stage & &

When all of the input signals of such a setting stage &S are L, theoutput signals thereof are likewise L. Consequently, the output signalof the respective OR/NOT- stage V is 0. Since one of the inputs of thesetting stage 8:, has applied to it the output signal E of therespective auxiliary store, this signal, too, has to he L.

The output signal H of the same auxiliary store must thus also be 0.This signal is applied to the AND-circuit & which is identified as anerasing stage. Consequently, there will appear at the output of thisstage & another signal 0. All of the input signals of the respective OR/NOT-circuit v will be 0 (assuming that the erase signal L is also equalto O), as a result of which the output signal of the OR/NOT-circuit v isL. This signal L is fed back to the OR/NOT-circuit v The output of thisstage v was already 0, due to the setting thereof, and this signal atthe output of OR/NOT-cireuit v remains at O in view of the signal Lapplied from the output of the OR/ NOT-circuit v;,. This signal 0 isapplied to the OR/NOT- circuit v So long as the signal at the output ofAND- circuit & and the erase signal are 0, the output signal of theOR/NOT-circuit 1 will be L, and becomes 0 only when all of the inputsignals applied to the AND-circuit 8 are L or when the erase signal Lbecomes equal to L. Thus, this holding condition is interrupted when allof the input signals applied to the AND-circuit 8: (this being the erasestage) are L.

The setting by the AND-circuit & and the erasing by the AND-circuit &takes place in an analogous manner in the case of the auxiliary store SIt will now be shown, with reference to the stage representing thebinary digit 2 that the outputs A and A will always be antivalent. Theanalysis is carried out at the main store S, of the binary digit 2 Theoutput of the OR/NOT-circuit V is referenced a,, and it will be shownthat a is always antivalent with respect to A Let it be, assumed thatthe output A is L. This means that the input signals of theOR/NOT-circuit v are 0, including the signal in line 2. In that case,however, the signal a will also be equal to 0 and hence antivalent to AIf, conversely, the signal at output A, is 0, at least one of the inputsof the OR/NOT-circuit v has to have a signal L applied to it. If theinput via line 2 is at L, the signal a is at L, so that the antivalenceis again proven.

Assuming next that it is the input via line 1 which is at,

L, then all inputs of the AND-circuit & have to be at L, including theoutput signal H so that the input line 7 of the OR/NOT-circuit v has tohave the signal L applied to it, as a result of which the output h is 0.This last-mentioned signal is applied to the AND-circuit 8: whose outputsignal is therefore 0, as is the signal applied to the input line 4 ofthe OR/NOT-circuit v (the input 3 is 0, since it was assumed that A =0)and the signal at output a; is therefore L, and is thus in this case,too, antivalent to the signal A The forward counting counter of FIGURE 3operates in accordance with the following logic functions:

( i-1 1-1 1) VB 1 1-1 1-18 I) 1 FIGURE 4 is a schematic circuit diagramof a forward counting counter which is provided with means by which thecounter can be preset. The counter is provided with inputs at the mainand auxiliary stores which allow the erase signal to be applied. Itshould be noted that these inputs are not absolutely essential if thecounter is to be used under conditions where there is no need rapidly toerase, i.e., to reset, the counter. In practice, however, it is oftenrequired, in the case of a presettable counter, that an erase signal betriggered after the counter has reached a predetermined count, whicherase signal is to erase the counter as quickly as possible. Thepresetting takes place via respective AND-circuits 8: & 8: & formingpart of the respective main stores. These AND-circuits have a respectivepresetting signal k and a common clear-forpresetting signal 1 applied tothem. The counter further includes, with each auxiliary store beginningwith store S an AND-circuit 8: 8: which also serve for presetting, theselast-mentioned AND-circuits being needed in order that the auxiliarystores assume the state which they would have assumed had the counterstarted to count from zero up to the value to which the counter ispreset. This result is brought about because these AND-circuits &' arecontrolled by the outputs of the main stores.

The counter of FIGURE .4 operates in accordance with logic functionsbasically similar to those of the counter of FIGURE 1 but supplementedas follows:

. v(A &A &f)=H

. v(A &A &f)=H

v(A &A &f)=H The dotted lines mean that the remaining setting andholding conditions of the counter of FIGURE 1 remain unchanged. It willthus be seen that the counter of FIG- URE 4 differs from that of FIGURE1 in that the counter of FIGURE 1 includes the additional element (f&k),and that the clear-for-counting signal Z2 is included in the settingcondition for all of the main stores. Also, the

auxiliary stores, except the lowest-order one, have an additional.holding condition. While this holding condition may be dispensed with inthe case of the digit 2 it is needed for all binary digits beginningwith 2 FIGURE 5 is a time plot showing the operation of the presettablecounter of FIGURE 4. Here it is assumed that the counting command signal2 is formed in a store which is set by a signal 2, and erased by asignal 2,, which signals Z and z may, for example, be produced by meansof a suitable keying device. The signal 1 appears after the erasing andprior to the start of the counting operation. This can be done, forinstance, in such a way that a signal m is set in a store by means ofthe erase signal L and is erased by the appearance of the signal 2.Within the time interval during which the signal in appears, after,however, the signal L has itself been erased, the signal 1 can appear,for example, by the actuation of a separate key which produces thesignal 1 The A-signals are then produced by the presetting settingstages of the main stores, and the presettiug setting stages of theauxiliary stores see to it that the H-signals will be such that, uponthe appearance of the first t signal that follows the appearance of theclear-for-counting signal z =L, the counter continues to count from thecount to which it has been preset. The lower part of the time plot ofFIGURE 5 also shows the K-signals put out by the main stores, theselast-mentioned signals representing a backward counting operation, inwhich the countdown is begun from a number C. This number C is thedifference between the highest number the counter can assume and thenumber to which the counter has been preset.

FIGURE 6 shows a four-digit binary counter which counts backward, theoutput of the counter appearing at the A-outputs of the main stores. Thelowest-order stage 2 again comprises a main store and an auxiliarystore, each of which has one input setting stage 8: and two inputholding stages 8%. The main stores and auxiliary stores of the otherbinary digits each have one input setting stage & and three inputholding stages & A comparison between the counters of FIGURES 1 and 6will show that each comprises the same number of components.

The backward counting counter of FIGURE 6 operates in accordance withthe following logi functions:

FIGURE 7 shows a backward counting binary counter which is modified inthe same manner as the counter of FIGURE 3, and the i stages, i.e., thestages other than the lowest-order stage, of the counter of FIGURE 7have main and auxiliary stores whose logic functions are as follows:

FIGURE 8 is a time plot showing the operation of two backward countingbinary counters of FIGURES 6 and 7. It will be seen that here, too, theoutput signals H change precisely at the middle of the output signals ofthe respective main stores and in the middle of the time intervalbetween two output signals of the respective main store. The lower partof FIGURE 8 shows the signals appearing at the K-outputs of the mainstores, which represent the forward counting operation.

FIGURE 9 shows one decade of a forward counting decimal counter which isderived from the binary counter of FIGURE 1. The lowest-order counterstage remains unchanged, with the logic functions of the modifiedhigher-order counter stages 2 2 2 being as follows:

FIGURE 10 is a time plot showing the operation of the decimal counter ofFIGURE 9. As is apparent from the time plot, the first change of stateof the H-signals (this being the appearance of the H-signals) occurs inthe middle of the respective A-signals; however, due to the fact thatsix of the possible counts are suppressed (only ten of the possiblecounts of the four-digit binary stage being needed to provide one decadeof the decimal coun ter), the second change of state, i.e., thedisappearance of the H-signals of the counter stages 2 2 2 does notalways occur in the middle of the time interval between two A-signals ofthe respective main store, so that, in the case of the decimal counter,the second change of state may be considered as occurring at leastgenerally in the middle of the time interval in question.

It will be understood that the above description of the presentinvention is susceptible to various modifications, changes, andadaptations, and the same are intended to be comprehended within themeaning and range of equivalents of the appended claims.

What is claimed is:

1. A static counter for counting forward or backward and controlled bycounting signals and auxiliary counting signals which do not changetheir state simultaneously, said counter comprising, in combination:

(a) plurality of binary counter stages each incorporating a main storeand an auxiliary store which put out signals A and H, respectively, eachstore having input stage means; and

(b) means interconnecting each i (i=1, 2, 3, counter stage with the (i1)counter stage for causing the output signal H produced by the auxiliarystore of each counter stage to change its state in the middle of theoutput signal A produced by the main store of the respective counterstage and in the middle of the time interval between this output signalA of said main store and the subsequent output signal A of said mainstore, and for causing the signals which produce the outputs of eachmain store and auxiliary store and which are put out by the input stagemeans of the respective main and auxiliary stores, to overlap eachother.

2. A counter as defined in claim 1 wherein the input stage means of eachmain and auxiliary store of each i counter stage comprises one inputsetting stage and three input holding stages.

3. A counter as defined in claim 1 wherein, when said counting signalsand auxiliary counting signals are sigauxiliary stores of the counterstage each comprises one input setting stage and three input holdingstages.

4. A counter as defined in claim 1 wherein the input stage means of eachstore comprises one input setting stage and at least two input holdingstages.

5. A counter as defined in claim 1 wherein the input stage means of eachstore comprises one input setting stage and one input erase stage havingat least two inputs.

'6. A counter as defined in claim 1 wherein the input stage means ofeach main and auxiliary store of each i counter stage comprises oneinput setting stage and one input erase stage having three inputs.

7. A counter as defined in claim 2 wherein said main and auxiliarystores of each 1 counter stage have the following logic functions:

( i i 1 i 1) 1 1) (Hi 1- 1) V i 1- 1 1 8. A counter as defined in claim3 wherein said main and auxiliary stores of said 0 counter stage, whenthe counter is controlled by said signals t have the following logicfunctions:

0 81A &z v (Ho 0 Zo) 0 3 22) 0 and, when the counter is controlled bysaid signals 1- 7 have the following logic functions:(TI&TZ&HQ&Z2)V(AO&FO&E)V

(A &? & L v (A &,1 &f) :A

('T' stT st/i szzpvqr alr srzpv (HQ&T2&Z2) V (H0&T1&Z2) =H0 9. A counteras defined in claim 6 wherein said main and auxiliary stores of each icounter stage have the following logic function:

:10. A counter as defined in claim 1, further including means forenabling the counter to be preset, said presetting means comprising:

(1) a plurality of input logic circuits connected, respectively, to allof the main stores and a plurality of further input logical circuitsconnected, respectively, to all of the auxiliary stores beginning withthe binary digits 2 (2) means for applying a respective presettingsignal to each of said input logic circuits connected to said mainstores;

(3) means for applying a common clear-for-presetting signal to all ofsaid input logic circuits connected to said main stores; and

(4) means for applying the output signals of said main stores to saidinput logic circuits connected to said auxiliary stores for causing saidauxiliary, stores to assume states which they would have assumed had thecounter counted from zero to the value to which the counter is preset.

11. A presettable counter as defined in claim 10 wherein said main andauxiliary stores of the 0 and each 1 counter stage have the followinglogic functions:

14. A static counter for counting forward or backward and controlled bycounting signals and auxiliary counting signals which do not changetheir state simultaneously, said counter comprising, in combination:

(a) a plurality of binary counter stages each incorporating a main storeand an auxiliary store which put out signals A and H, respectively, eachstore having input stage means, said plurality of binary counter stagesbeing arranged to form decades which put out decimal numbers in binarycoded form; and

(b) means interconnecting each i (i=1, 2, 3,

counter stage with the (i--1)' counter stage for causing the outputsignal H produced by the auxiliary store of each counter stage to changeits state in the middleof the output signal A produced by the main storeof the respective counter stage and at least generally in the middle ofthe time interval between this output signal A of said main store andthe subsequent output signal A of said main store, and for causing thesignals which produce the outputs of each main store and auxiliary storeand which are put out by the input stage means of the respective mainand auxiliary stores, to overlap each other.

15. A decimal counter as defined in claim 14, wherein the counter stagesfor the binary digits 2 2 2 of a decade have the following logicfunctions:

No references cited.

ARTHUR GAUSS, Primary Examiner.

S. MILLER, Assistant Examiner,

1. A STATIC COUNTER FOR COUNTING FORWARD OR BACKWARD AND CONTROLLED BYCOUNTING SIGNALS AND AUXILIARY COUNTING SIGNALS WHICH DO NOT CHANGETHEIR STATE SIMULTANEOUSLY, SAID COUNTER COMPRISING, IN COMBINATION: (A)PLURALITY OF BINARY COUNTER STAGES EACH INCORPORATING A MAIN STORE ANDAN AUXILIARY STORE WHICH PUT OUT SIGNALS A AND H, RESPECTIVELY, EACHSTORE HAVING INPUT STAGE MEANS; AND (B) MEANS INTERCONNECTING EACH JTH(J=1, 2, 3,...) COUNTER STAGE WITH THE (J-1)TH COUNTER STAGE FOR CAUSINGTHE OUTPUT SIGNAL H PRODUCED BY THE AUXILIARY STORE OF EACH COUNTERSTAGE TO CHANGE ITS STATE IN THE MIDDLE OF THE OUTPUT SIGNAL A PRODUCEDBY THE MAIN STORE OF THE RESPECTIVE COUNTER STAGE AND IN THE MIDDLE OFTHE TIME INTERVAL BETWEEN THIS OUTPUT SIGNAL A OF SAID MAIN STORE ANDTHE SUBSEQUENT OUTPUT SIGNAL A OF SAID MAIN STORE, AND FOR CAUSING THESIGNALS WHICH PRODUCE THE OUTPUTS OF EACH MAIN STORE AND AUXILIARY STOREAND WHICH ARE PUT OUT BY THE INPUT STAGE MEANS OF THE RESPECTIVE MAINAND AUXILIARY STORES, TO OVERLAP EACH OTHER.